The code examples for FPGA SIMULATION are now on GitHub. Enjoy!

fpgasimulation - Example files for the book FPGA SIMULATION

So this is embarrassing.

I lost my only PDF copy of FPGA Simulation.

I'll bet one of you has one.


Could you email it to


See More

Hah! Reached 1K likes.

Launching CHILD NOT FOUND at Brookline Booksmith on Monday June 6 at 7PM #craftbeer #biscotti

In other news, I also write mysteries under the name Ray Daniel. My first mystery in the Tucker series of mysteries is named TERMINATED (Midnight Ink) and is the first book in a three book deal.

Tucker is an engineer who uses his debugging mindset to solve murders.

First-person Wise-cracking Boston-based mystery.

Thanks to David Amor for showing me

The site allows you to try out simulators. It should work with the examples from FPGA SIMULATION. I've put up the first example from The UVM Primer as a test.

Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

I just thought I'd let you all know that I am now officially a published mystery writer. My new novel TERMINATED is part of a three-book deal with Midnight Ink. It features Tucker, an engineer who solves crimes (in this case his wife's murder.) You can learn more below. I hope you enjoy the book!

Ray Salemi (aka Ray Daniel)

First-person Wise-cracking Boston-based mystery.

Today I gave Amazon and Createspace a chance to make a Kindle Book out of FPGA Simulation. They did a good job with the text, but lost all the figures and code examples. Bummer.

If you are considering using the Universal Verification Methodology (UVM) to implement the ideas in FPGA Simulation, you might like my new book: THE UVM PRIMER.

The book uses downloadable code examples that are explained on Youtube and a related discussion group to answer your questions.

The UVM Primer teaches you the basics of the UVM through examples and easy-to-understand language.

I'm working on a new book and I'm trying to come up with an antonym to the word "concrete."

If coding in a "concrete" style creates programs that set and are harder to change over time, what would be a good word for writing programs that are easier to change over time. I'm currently going with "flexible"

Any better options?

You can see videos of the seven steps for FPGA Simulation at the Verification Academy.

I am now on the Verification Academy presenting Step 1 of the seven steps of verification : Code Coverage. You can sign up for the Code Coverage

One of my articles was published this week in EEWeb. The title is The Bug Processing Machine.


Happy New Year!

This is the time of year where we look back at how we did in the previous year (or decade) and resolve to do better. With that in mind, I recommend three

Very cool site that teaches VHDL.

We developed the following tutorial based on the philosophy that the beginning student need not understand the details of VHDL -- instead, they should be able to modify examples to build the desired basic circuits. Thus, they learn the importance of HDL-based digital design, without having to learn...
The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation. This raises the question of

Remember that you can download all the FPGA code examples from this link:

This page contains links to coding examples. All the files are .zip. They can be unzipped in Windows with the built in decompression tool, and they can be

FPGA Simulation Tip

Hi <<First Name>> I'm just writing to let you know that I've decided to move the FPGA Simulation Tips conversation to a Facebook Page. I believe this gives us the opportunity for a more interactive experience as we discuss FPGA Simulation. I hope that you will "Like" the page! https://www.face...

Merry Christmas!

Introduces the concepts of monitors in a test bench.

Use what you know about VHDL to learn the basics of SystemVerilog.

The debate between Verilog and VHDL has raged for twenty years, and as an AE for Mentor Graphics I still get questions about which is the better language. The answer to this question has become clear: both languages work for RTL design.